Phase Locked Loops (PLLs) are widely used for synchronizing digital clock signals. Digital integrated circuits make use of PLLs in compensating for internal signal-to-signal delays also known as “skews”. Skew compensations are often critical to the functioning of the circuit, especially when fast clock speeds are involved. The clock signal in high-speed synchronous digital integrated circuits is particularly sensitive to skews, and a great deal of attention is therefore paid to skew compensations in the distribution of this signal. In addition, the internal clock is generally required to be synchronized to an external clock source. Large integrated circuits make of clock tree structures to provide a structured and balanced distribution of the clock across the device.
The internal delays of signals in integrated circuits arise from delays contributed by circuit elements as well as delay contributed by the physical path traversed by the signal. Signal path delays are significantly influenced by the physical layout of the device. In signal skew compensation applications it is therefore necessary for the PLL to map the internal signal delays of the two signals to be synchronized. As the signal delays are dependant on the physical layout, the mapping is layout dependant. The design of the PLL block in the integrated circuit is therefore delayed until the rest of the device has been completed. Considering the importance of reducing the development cycle time for integrated circuits it would be desirable to have a mechanism that could enable the PLL design to overlap the design of the remainder of the device.
PLL operation requires a continuous operation of the clock sources that are required to be synchronized. In the conventional practice when there is no SLEEP modes in a circuit, the point chosen for the feedback is at the leaf of the clock tree as shown in FIG. 1 of the accompanying drawings. But for the circuits with sleep mode as shown in FIG. 2 of the accompanying drawings, during the sleep mode the clock terminates from point 206 onwards, which in turn makes the feedback loop ineffective, as there is no signal activity at point 208. A detailed description of FIGS. 1 and 2 has been given below after the description of the accompanying drawings.
U.S. Pat. No. 6,023,180 discloses a clock compensation circuit, which provides a PLL circuit without utilizing any analog circuitry (e.g. VCO etc.). In this patent, the digital components available in any Application Specific Integrated Chip (ASIC) vendor's library are utilized for realization of the equivalent PLL functions. The disclosed PLL includes a clock tree, a reference clock, a phase detector for detecting relative phase information of the clock tree and the reference clock, a controller coupled to the phase detector for determining and controlling the amount of delay necessary to shift the output of the clock tree in phase with the reference clock, and a programmable delay logic coupled to the controller. The programmable delay logic comprises a string of delay elements that selectively determine the amount of delay introduced. This patent also discloses providing the feedback to the PLL from the point at a leaf cell, and hence this PLL is unable to function during SLEEP mode of the circuit.